دانلود کتاب طراحی فیزیکی VLSI از پارتیشن بندی نمودار تا بسته شدن زمان

Physical design of integrated circuits remains one of the most interesting and challenging arenas in the field of electronic design automation. The ability to integrate more and more devices on our silicon chips requires the algorithms to continuously scale up. Nowadays, we can integrate 12 billion transistors on a single 5 nm-technology chip. This number will continue to scale up for the next couple of technology generations, requiring more transistors to be automatically placed on a chip and connected. In addition, more and more of the delay is contributed by the wires that interconnect the devices on the chip. This has a profound effect on how physical design flows need to be put together. In the 1990s, it was safe to assume that timing goals of the design could be reached once the devices were placed well on the chip. Today, one does not know whether the timing constraints can be satisfied until the final routing has been completed.